Graph partitioning applied to the logic testing of combinational circuits

被引：0
|
作者：
机构：
来源：
Discrete Appl Math | / 1-3卷 / 131期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] Reducing the logic-level of the combinational circuits
    Ye, Yizheng
    Zeng, Xianjun
    Zhang, Yan
    Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design & Computer Graphics, 1997, 9 (01):
  • [22] On evolution of relatively large combinational logic circuits
    Stomeo, E
    Kalganova, T
    Lambert, C
    Lipnitsakya, N
    Yatskevich, Y
    2005 NASA/DOD CONFERENCE ON EVOLVABLE HARDWARE (EH-2005), PROCEEDINGS, 2005, : 59 - 66
  • [23] Checking Combinational Circuits by the Method of Logic Complement
    M. Goessel
    A. V. Morozov
    V. V. Sapozhnikov
    Vl. V. Sapozhnikov
    Automation and Remote Control, 2005, 66 : 1336 - 1346
  • [24] ON PATH SELECTION IN COMBINATIONAL LOGIC-CIRCUITS
    LI, WN
    REDDY, SM
    SAHNI, SK
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (01) : 56 - 63
  • [25] Optimization of Combinational Logic Circuits with Genetic Programming
    Karakatic, S.
    Podgorelec, V.
    Hericko, M.
    ELEKTRONIKA IR ELEKTROTECHNIKA, 2013, 19 (07) : 86 - 89
  • [26] Combinational Equivalence Checking for Threshold Logic Circuits
    Gowda, Tejaswi
    Vrudhula, Sarma
    Konjevod, Goran
    GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI, 2007, : 102 - 107
  • [27] RING TESTING OF COMBINATIONAL-CIRCUITS
    LITIKOV, IP
    AUTOMATION AND REMOTE CONTROL, 1983, 44 (07) : 949 - 955
  • [28] Arbitrary Error Detection in Combinational Circuits by using Partitioning
    Keren, Osnat
    Levin, Ilya
    Ostrovsky, Vladimir
    Abramov, Beni
    23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 361 - +
  • [29] Test input generation for supply current testing of bridging faults in bipolar combinational logic circuits
    Kuchii, T
    Hashizume, M
    Tamesada, T
    1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS, 1998, : 14 - 18
  • [30] Design of Combinational Logic circuits for Low power Reversible Logic circuits in Quantum Cellular Automata
    Anand, I. Vivek
    Kamaraj, A.
    2014 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2014,
12345