A 512 16-b bit-serial sorter chip

被引:0
|
作者
机构
[1] Afghahi, M.
来源
Afghahi, M. | 1600年 / 26期
关键词
Bit-Serial Sorter Chip - Highly Pipelined Bit-Serial Architecture - Sorting Algorithm;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
相关论文
共 50 条
  • [41] HIGH-PERFORMANCE BIT-SERIAL ADDERS AND MULTIPLIERS
    BI, G
    JONES, EV
    IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1992, 139 (01): : 109 - 113
  • [42] Distance transform algorithm for bit-serial SIMD architectures
    Takala, JH
    Viitanen, JO
    COMPUTER VISION AND IMAGE UNDERSTANDING, 1999, 74 (02) : 150 - 161
  • [43] A BIT-SERIAL VLSI RECEPTIVE-FIELD ACCUMULATOR
    STROHBEHN, K
    ANDREOU, AG
    PROCEEDINGS OF THE IEEE 1989 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1989, : 323 - 328
  • [44] HDL Based Implementation of NxN Bit-Serial Multiplier
    Akhter, Shamim
    Chaturvedi, Saurabh
    2014 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN), 2014, : 470 - 474
  • [45] Optimizing Bit-Serial Matrix Multiplication for Reconfigurable Computing
    Umuroglu, Yaman
    Conficconi, Davide
    Rasnayake, Lahiru
    Preusser, Thomas B.
    Sjalander, Magnus
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2019, 12 (03)
  • [46] A bit-serial systolic algorithm and VLSI implementation for RSA
    Zhang, CN
    Xu, Y
    Wu, CC
    1997 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING, VOLS 1 AND 2: PACRIM 10 YEARS - 1987-1997, 1997, : 523 - 526
  • [47] SORTING WITHOUT EXCHANGES ON A BIT-SERIAL SYSTOLIC ARRAY
    MEGSON, GM
    IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS, 1990, 137 (05): : 345 - 352
  • [48] BEHAVIORAL TO STRUCTURAL TRANSLATION IN A BIT-SERIAL SILICON COMPILER
    HARTLEY, RI
    JASICA, JR
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (08) : 877 - 886
  • [49] Bit-serial architecture for rank order and stack filters
    Hiasat, A
    Hasan, O
    INTEGRATION-THE VLSI JOURNAL, 2003, 36 (1-2) : 3 - 12
  • [50] An area-efficient bit-serial integer multiplier
    Schimmler, M
    Schmidt, B
    Lang, HW
    Heithecker, S
    VLSI'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON VLSI, 2003, : 131 - 137