HDL Based Implementation of NxN Bit-Serial Multiplier

被引：0

作者：

Akhter, Shamim ^{[1
]}

Chaturvedi, Saurabh ^{[1
]}

机构：

[1] Jaypee Inst Informat Technol, Dept Elect & Commun Engn, Noida, India

来源：

2014 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2014年

关键词：

Binary multiplication; Serial bit multiplier; Parallel multiplier; Partial product; HDL; FPGA;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The paper proposes a systematic design methodology for bit-serial multiplication. The proposed approach is a modified method for performing traditional multiplication. This paper presents a general technique for NxN bit-serial multiplication used in signal processing. HDL implementation and simulation of 4x4 bit-serial multiplier is discussed. Synthesis is performed using Xilinx ISE with Virtex-4 ML402 FPGA board.

引用

页码：470 / 474

页数：5

共 50 条

[1] ON A BIT-SERIAL INPUT AND BIT-SERIAL OUTPUT MULTIPLIER
GNANASEKARAN, R
IEEE TRANSACTIONS ON COMPUTERS, 1983, 32 (09) : 878 - 880
[2] BIT-SERIAL MODULAR MULTIPLIER
TOMLINSON, A
ELECTRONICS LETTERS, 1989, 25 (24) : 1664 - 1664
[3] BIT-SERIAL MULTIPLIER BASED ON JOSEPHSON LATCHING LOGIC
Moopenn, A.
Arambula, E. R.
Lewis, M. J.
Chan, H. W.
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, 1993, 3 (01) : 2698 - 2701
[4] The asynchronous counterflow pipeline bit-serial multiplier
Tosic, MB
Stojcev, MK
Maksimovic, DM
Djordjevic, GL
JOURNAL OF SYSTEMS ARCHITECTURE, 1998, 44 (12) : 985 - 1004
[5] A Hardware Implementation of Word-Parallel Bit-Serial Polynomial Basis Multiplier
Cho, Yong Suk
Choi, Jae Yeon
COMPUTER APPLICATIONS FOR GRAPHICS, GRID COMPUTING, AND INDUSTRIAL ENVIRONMENT, 2012, 351 : 176 - +
[6] On implementation of fast, bit-serial loops
Vesterbacka, M
Palmkvist, K
Manhammar, L
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 1996, : 190 - 193
[7] An area-efficient bit-serial integer multiplier
Schimmler, M
Schmidt, B
Lang, HW
Heithecker, S
VLSI'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON VLSI, 2003, : 131 - 137
[8] RECONFIGURABLE TESTABLE BIT-SERIAL MULTIPLIER FOR DSP APPLICATIONS
BAYOUMI, MA
YANG, CH
IEE PROCEEDINGS-E COMPUTERS AND DIGITAL TECHNIQUES, 1989, 136 (06): : 517 - 523
[9] Bit-Serial multiplier based Neural Processing Element with Approximate adder tree
Jo, Cheolwon
Lee, KwangYeob
2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020), 2020, : 286 - 287
[10] THE VLSI IMPLEMENTATION OF A REED-SOLOMON ENCODER USING BERLEKAMP BIT-SERIAL MULTIPLIER ALGORITHM
HSU, IS
REED, IS
TRUONG, TK
WANG, K
YEH, CS
DEUTSCH, LJ
IEEE TRANSACTIONS ON COMPUTERS, 1984, 33 (10) : 906 - 911

← 1 2 3 4 5 →