HDL Based Implementation of NxN Bit-Serial Multiplier

被引：0

作者：

Akhter, Shamim ^{[1
]}

Chaturvedi, Saurabh ^{[1
]}

机构：

[1] Jaypee Inst Informat Technol, Dept Elect & Commun Engn, Noida, India

来源：

2014 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND INTEGRATED NETWORKS (SPIN) | 2014年

关键词：

Binary multiplication; Serial bit multiplier; Parallel multiplier; Partial product; HDL; FPGA;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

The paper proposes a systematic design methodology for bit-serial multiplication. The proposed approach is a modified method for performing traditional multiplication. This paper presents a general technique for NxN bit-serial multiplication used in signal processing. HDL implementation and simulation of 4x4 bit-serial multiplier is discussed. Synthesis is performed using Xilinx ISE with Virtex-4 ML402 FPGA board.

引用

页码：470 / 474

页数：5

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