PIMLC: Logic Compiler for Bit-serial Based PIM

被引：0

作者：

Tang, Chenyu ^{[1
]}

Nie, Chen ^{[1
]}

Qian, Weikang ^{[2
,3
]}

He, Zhezhi ^{[1
]}

机构：

[1] Shanghai Jiao Tong Univ, Sch Elect Informat & Elect Engn, Shanghai, Peoples R China

[2] Shanghai Jiao Tong Univ, UM SJTU Joint Inst, Shanghai, Peoples R China

[3] Shanghai Jiao Tong Univ, MoE Key Lab AI, Shanghai, Peoples R China

来源：

2024 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, DATE | 2024年

基金：

中国国家自然科学基金; 国家重点研发计划;

关键词：

PERFORMANCE;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Recently, the bit-serial-based processing-in-memory (PIM) has evolved as a promising solution to enhance the computing performance of data-intensive applications, due to its high performance and programmability. However, it is absent that a compiler can automatically convert an arbitrary Boolean function (generic workload) into PIM instructions, with optimized scheduling w.r.t. the varying hardware resource and specification. To fill the gap, we develop a logic compiler for bit-serial-based PIM (PIMLC). In PIMLC, we propose a workload-resource-aware scheduling to minimize the execution latency of a given parallel workload. Thanks to PIMLC, PIM can achieve 15.55x and 19.03x speedup (geo-mean) for SRAM- and ReRAM-PIM respectively, compared to the naive scheduling of prior work. PIMLC is publicly available at: https://github.com/IntelligentComputing-Research-Group/PIMLC.

引用

页数：6

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