THE VLSI IMPLEMENTATION OF A REED-SOLOMON ENCODER USING BERLEKAMP BIT-SERIAL MULTIPLIER ALGORITHM

被引：0
|
作者：
HSU, IS [1 ]
REED, IS [1 ]
TRUONG, TK [1 ]
WANG, K [1 ]
YEH, CS [1 ]
DEUTSCH, LJ [1 ]
机构：
[1] CALTECH,JET PROP LAB,PASADENA,CA 91109
来源：
IEEE TRANSACTIONS ON COMPUTERS | 1984年 / 33卷 / 10期
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D O I：
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中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：906 / 911
页数：6
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