Efficient sorting architecture for radix-4 FFT in FPGA

The novel sorting architecture of the fast Fourier transform (FFT) processor is presented based on radix-4 decimation-in-time algorithm. By combining both the pipeline and parallel schemes, the proposed radix-4 butterfly uses three real multipliers and nine real adders, which leads to reduce conventional multipliers by 75%. The processor based on field programmable gate array (FPGA) can operate at 100 MHz and calculate the 1024 floating-point complex FFT in 51.29 μs. So it satisfies the needs of both small area and high speed. Furthermore, since the sorting architecture can be easily upgraded for radix-8 or radix-16 FFT algorithm, and does not increase the clocks required for computing a radix-4 butterfly, it will be more efficient for the high radix.