An efficient implementation of rotational radix-4 CORDIC based FFT processor

A new technique for implementing low power FFTs based on memory less Z path eliminated CORDIC is proposed in this paper. The vector rotation in the x/y plane can be realized by rotating a vector through a series of elementary angles. These elementary angles are chosen such that the vector rotation through each of them may be approximated easily with a simple shift and add operation, and their algebraic sum approaches the required rotation angle. This can be exercised by CORDIC (CO-ordinate Rotation Digital Computer) algorithm in rotation mode. Pipelined architecture by pre computation of direction of micro rotation, radix-4 number representation, and the angle generator has been processed in terms of hardware complexity, iteration delay and memory reduction. The proposed algorithm also exercises an addressing scheme and the associated angle generator logic in order to eliminate the ROM usage for bottling the twiddle factors. It incorporates parallelism and pipe line processing. The latency of the system is n/2 clock cycles. The throughput rate is one valid result per eight clock cycles. The approached architecture for radix-4, 16-bit precision and 16 -point FFT was implemented on FPGA platform virtex 5 and simulated to validate the results. This contributes to the minimization of the dynamic power consumption of the proposed system to 28.52mW at 100MHz and 5.70mW at 20MHz with the maximum operating frequency of 450.564MHZ.