Design of a 32-Bit CMOS fixed/floating point multiplier

被引：0

作者：

Yu, D.S. ^{[1
]}

Shen, X.B. ^{[1
]}

机构：

[1] Xi'an Microelectron. Technol. Inst., Xi'an 710065, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2001年 / 22卷 / 01期

关键词：

Adders - CMOS integrated circuits - Trees (mathematics);

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Wallace tree multipliers are very difficult to implement due to their complex routing requirement. A novel tree structure was presented, which required simpler wiring than ZM trees and OS trees, and a novel CLA adder with 30% faster than the conventional one was proposed to enhance the speed performance. The multiplier is fabricated with 1.5 μm CMOS technology, which can perform a 32-bit floating point multiplication (based on the proposed IEEE P754 standard format) and a 32-bit fixed point multiplication in 56 ns and 76 ns respectively.

引用

页码：91 / 95

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