Design of a 32-Bit CMOS fixed/floating point multiplier

被引：0

作者：

Yu, D.S. ^{[1
]}

Shen, X.B. ^{[1
]}

机构：

[1] Xi'an Microelectron. Technol. Inst., Xi'an 710065, China

来源：

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors | 2001年 / 22卷 / 01期

关键词：

Adders - CMOS integrated circuits - Trees (mathematics);

D O I：

暂无

中图分类号：

学科分类号：

摘要：

Wallace tree multipliers are very difficult to implement due to their complex routing requirement. A novel tree structure was presented, which required simpler wiring than ZM trees and OS trees, and a novel CLA adder with 30% faster than the conventional one was proposed to enhance the speed performance. The multiplier is fabricated with 1.5 μm CMOS technology, which can perform a 32-bit floating point multiplication (based on the proposed IEEE P754 standard format) and a 32-bit fixed point multiplication in 56 ns and 76 ns respectively.

引用

页码：91 / 95

共 50 条

[21] 32-bit constant (k) coefficient multiplier
Al-Khalili, AJ
Zaman, NU
IEEE REGION 10 INTERNATIONAL CONFERENCE ON ELECTRICAL AND ELECTRONIC TECHNOLOGY, VOLS 1 AND 2, 2001, : 306 - 308
[22] Research and implementation of a 32-bit asynchronous multiplier
Li, Yong
Wang, Lei
Gong, Rui
Dai, Kui
Wang, Zhiying
Jisuanji Yanjiu yu Fazhan/Computer Research and Development, 2006, 43 (12): : 2152 - 2157
[23] A CMOS FLOATING POINT MULTIPLIER
UYA, M
KANEKO, K
YASUI, J
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) : 697 - 702
[24] A CMOS FLOATING POINT MULTIPLIER
UYA, M
KANEKO, K
YASUI, J
ISSCC DIGEST OF TECHNICAL PAPERS, 1984, 27 : 90 - &
[25] An energy-efficient 32-bit multiplier architecture in 90-nm CMOS
Mehmood, Nasir
Hansson, Martin
Alvandpour, Atila
24TH NORCHIP CONFERENCE, PROCEEDINGS, 2006, : 35 - +
[26] TRADE MEMORY MANAGEMENT FOR FLOATING-POINT MATH ON 32-BIT MICROPROCESSORS
BURSKY, D
ELECTRONIC DESIGN, 1985, 33 (29) : 54 - 54
[27] MOTOROLA DSP96002 32-BIT FLOATING-POINT DSP
不详
EDN, 1995, 40 (10) : 68 - 68
[28] A 32-bit logarithmic arithmetic unit and its performance compared to floating point
Coleman, JN
Chester, EI
14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1999, : 142 - 151
[29] The research on optimization techniques of 32-bit floating-point RISC microprocessor
Sun, HJ
Shao, ZB
Zou, G
Zhao, N
Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005, : 63 - 66
[30] BUILDING 32-BIT SYSTEMS - MMUS AND FLOATING-POINT WILL BE BOARDS FOR NOW
GOLD, M
ELECTRONIC DESIGN, 1984, 32 (09) : 27 - 27

← 1 2 3 4 5 →