Power and performance comparison of crossbars and buses as on-chip interconnect structures

被引：0
|
作者：
Pennsylvania State Univ, University Park, United States [1 ]
机构：
来源：
Conf Rec Asilomar Conf Signals Syst Comput | / 378-383期
关键词：
Compendex;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
12
引用
收藏
相关论文
共 50 条
  • [1] A driver load model for capacitive coupled on-chip interconnect buses
    Tahedl, M
    Pfleiderer, HJ
    INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, 2003, : 101 - 104
  • [2] Low power encoding for coupled on-chip buses
    Ghoneima, M
    Ismail, Y
    Proceedings of the 46th IEEE International Midwest Symposium on Circuits & Systems, Vols 1-3, 2003, : 552 - 555
  • [3] THERMAL-STABILITY OF ON-CHIP COPPER INTERCONNECT STRUCTURES
    GUTMANN, RJ
    CHOW, TP
    KALOYEROS, AE
    LANFORD, WA
    MURAKA, SP
    THIN SOLID FILMS, 1995, 262 (1-2) : 177 - 186
  • [4] On-chip interconnect simulation of parasitic capacitances in periodic structures
    Nentchev, A
    Sabelka, R
    Wessner, W
    Selberherr, S
    MODELLING AND SIMULATION 2005, 2005, : 420 - 424
  • [5] Noise-aware power optimization for on-chip interconnect
    Kim, KW
    Jung, SO
    Narayanan, U
    Liu, CL
    Kang, SM
    ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, : 108 - 113
  • [6] On-Chip Optical Interconnect
    Ohashi, Keishi
    Nishi, Kenichi
    Shimizu, Takanori
    Nakada, Masafumi
    Fujikata, Junichi
    Ushida, Jun
    Torii, Sunao
    Nose, Koichi
    Mizuno, Masayuki
    Yukawa, Hiroaki
    Kinoshita, Masao
    Suzuki, Nobuo
    Gomyo, Akiko
    Ishi, Tsutomu
    Okamoto, Daisuke
    Furue, Katsuya
    Ueno, Toshihide
    Tsuchizawa, Tai
    Watanabe, Toshifumi
    Yamada, Koji
    Itabashi, Sei-ichi
    Akedo, Jun
    PROCEEDINGS OF THE IEEE, 2009, 97 (07) : 1186 - 1198
  • [7] A Laser Power Management Method for On-Chip Photonic Interconnect
    Wang, Xiaolu
    Guo, Yiming
    Gu, Huaxi
    Wang, Kun
    2016 SEVENTH INTERNATIONAL GREEN AND SUSTAINABLE COMPUTING CONFERENCE (IGSC), 2016,
  • [8] Noise-aware power optimization for on-chip interconnect
    Kim, Ki-Wook
    Jung, Seong-Ook
    Narayanan, Unni
    Liu, C.L.
    Kang, Sung-Mo
    Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers, 2000, : 108 - 113
  • [9] Measuring and Modeling On-Chip Interconnect Power on Real Hardware
    Adhinarayanan, Vignesh
    Paul, Indrani
    Greathouse, Joseph L.
    Huang, Wei
    Pattnaik, Ashutosh
    Feng, Wu-chun
    PROCEEDINGS OF THE 2016 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION, 2016, : 23 - 33
  • [10] The effect of power islands on Delta-I noise, interconnect noise, and timing for wide, on-chip data-buses
    Deutsch, A
    Smith, HH
    Huang, HM
    Elfadel, A
    Electrical Performance of Electronic Packaging, 2004, : 303 - 306
12345