共 50 条
- [2] Power Management of Hybrid DRAM/PRAM-Based Main Memory [J]. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 59 - 64
- [3] PDRAM: A Hybrid PRAM and DRAM Main Memory System [J]. DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2009, : 664 - 669
- [4] An Optimal Page-Level Power Management Strategy in PCM–DRAM Hybrid Memory [J]. International Journal of Parallel Programming, 2017, 45 : 4 - 16
- [6] Power-Aware Variable Partitioning for DSPs with Hybrid PRAM and DRAM Main Memory [J]. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 405 - 410
- [10] AIMR: An Adaptive Page Management Policy for Hybrid Memory Architecture with NVM and DRAM [J]. 2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS), 2015, : 284 - 289