PDRAM: A Hybrid PRAM and DRAM Main Memory System

被引：0

作者：

Dhiman, Gaurav ^{[1
]}

Ayoub, Raid ^{[1
]}

Rosing, Tajana ^{[1
]}

机构：

[1] Univ Calif San Diego, Dept Comp Sci & Engn, La Jolla, CA 92093 USA

来源：

DAC: 2009 46TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2 | 2009年

基金：

美国国家科学基金会;

关键词：

Phase Change Memory; Energy Efficiency; Memory management;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, we propose PDRAM, a novel energy efficient main memory architecture based on phase change random access memory (PRAM) and DRAM. The paper explores the challenges involved in incorporating PRAM into the main memory hierarchy of computing systems, and proposes a low overhead hybrid hardware-software solution for managing it. Our experimental results indicate that our solution is able to achieve average energy savings of 30% at negligible overhead over conventional memory architectures.

引用

页码：664 / 669

页数：6

共 50 条

[1] Power Management of Hybrid DRAM/PRAM-Based Main Memory
Park, Hyunsun
Yoo, Sungjoo
Lee, Sunggu
[J]. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 59 - 64
[2] Power-Aware Variable Partitioning for DSPs with Hybrid PRAM and DRAM Main Memory
Liu, Tiantian
Zhao, Yingchao
Xue, Chun Jason
Li, Minming
[J]. PROCEEDINGS OF THE 48TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2011, : 405 - 410
[3] A Space Effective DRAM Adapter for PRAM-based Main Memory System
Lee, Do-Heon
Yoon, Su-Kyoung
Kim, Jung-Geun
Kim, Cheong-Gil
Kim, Shin-Dug
[J]. 2013 INTERNATIONAL CONFERENCE ON IT CONVERGENCE AND SECURITY (ICITCS), 2013,
[4] Power-Aware Variable Partitioning for DSPs With Hybrid PRAM and DRAM Main Memory
Liu, Tiantian
Zhao, Yingchao
Xue, Chun Jason
Li, Minming
[J]. IEEE TRANSACTIONS ON SIGNAL PROCESSING, 2013, 61 (14) : 3509 - 3520
[5] DH-LRU: Dynamic Hybrid LRU Caching Scheme for PRAM/DRAM Hybrid Main Memory
Ren, Yongjian
Xie, Hongtianchen
Jia, Gangyong
Zhang, Jilin
Yin, Yuyu
Wan, Jian
[J]. INTERNATIONAL JOURNAL OF GRID AND DISTRIBUTED COMPUTING, 2016, 9 (11): : 81 - 94
[6] Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU
Kim, Dongki
Lee, Sungkwang
Chung, Jaewoong
Kim, Dae Hyun
Woo, Dong Hyuk
Yoo, Sungjoo
Lee, Sunggu
[J]. 2012 49TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2012, : 888 - 896
[7] Sleep-Aware Variable Partitioning for Energy-Efficient Hybrid PRAM and DRAM Main Memory
Fu, Chenchen
Zhao, Mengying
Xue, Chun Jason
Orailoglu, Alex
[J]. PROCEEDINGS OF THE 2014 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED), 2014, : 75 - 80
[8] Exploiting page write pattern for power management of hybrid DRAM/PRAM memory system
School of Computer Science and Information Engineering, Zhejiang Gongshang University, Hangzhou
310018, China
不详
310027, China
[J]. J. Inf. Sci. Eng., 5 (1633-1646):
[9] Exploiting Page Write Pattern for Power Management of Hybrid DRAM/PRAM Memory System
Zhang, Tiefei
Xing, Jianguo
Zhu, Jixiang
Chen, Tianzhou
[J]. JOURNAL OF INFORMATION SCIENCE AND ENGINEERING, 2015, 31 (05) : 1633 - 1646
[10] Adaptive Wear-Leveling Algorithm for PRAM Main Memory with a DRAM Buffer
Park, Sung Kyu
Maeng, Min Kyu
Park, Ki-Woong
Park, Kyu Ho
[J]. ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2014, 13 (04)

← 1 2 3 4 5 →