共 50 条
- [41] Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2012, E95C (04): : 546 - 554
- [45] Improved power estimation for behavioral and gate level designs [J]. IEEE COMPUTER SOCIETY WORKSHOP ON VLSI 2001, PROCEEDINGS, 2001, : 102 - 107
- [46] Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance [J]. PROCEEDINGS OF THE 32ND GREAT LAKES SYMPOSIUM ON VLSI 2022, GLSVLSI 2022, 2022, : 77 - 83
- [48] Optimization of Dynamic Power Consumption in Multi-Tier Gate-Level Monolithic 3D ICs [J]. PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN ISQED 2016, 2016, : 29 - 34
- [49] Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM [J]. IET COMPUTERS AND DIGITAL TECHNIQUES, 2007, 1 (03): : 187 - 196
- [50] Digital Statistical Analysis Using VHDL Impact of Variations on Timing and Power Using Gate-Level Monte Carlo Simulation [J]. 2010 DESIGN, AUTOMATION & TEST IN EUROPE (DATE 2010), 2010, : 1007 - 1010