Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration

被引:0
|
作者
Taghipour, Pouya [1 ]
Granger, Eric [2 ]
Blaquiere, Yves [1 ]
机构
[1] Ecole Technol Super ETS, Dept Elect Engn, LaCIME, Montreal, PQ H3C 1K3, Canada
[2] Ecole Technol Super ETS, Dept Syst Engn, LIVIA, ILLS, Montreal, PQ H3C 1K3, Canada
来源
IEEE ACCESS | 2024年 / 12卷
基金
加拿大自然科学与工程研究理事会;
关键词
Accuracy; Predictive models; Analytical models; Costs; Codes; Training; Graph neural networks; Standards; Optimization; Logic; Electronic design automation (EDA); high-level synthesis (HLS); design space exploration (DSE); machine learning (ML); graph neural networks (GNN); field-programmable gate array (FPGA);
D O I
10.1109/ACCESS.2024.3509606
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Optimizing hardware accelerators in high-level synthesis (HLS) relies on design space exploration (DSE), which involves experimenting with different pragma options and trading off hardware cost and performance metrics (HCPMs) to identify Pareto-optimal solutions. The exponential growth of the design space, poor quality-of-results (QoR) estimation by HLS tools, and lengthy post-implementation runtime have made the HLS DSE process highly challenging and time-consuming. Automating this process could reduce time-to-market and associated development costs. Learning-based methods, particularly graph neural networks (GNNs), have shown considerable potential in addressing HLS QoR/DSE problems by modeling the mapping function from control data flow graphs (CDFGs) of HLS designs to their logic, enabling early estimation of QoR during the compilation phase of the hardware design flow. However, there is still a gap in terms of their prediction accuracy. Indeed, modeling HLS-related problems using GNNs that efficiently capture the complex patterns arising from applied pragmas and low-level characteristics of HLS specifications is challenging. This paper introduces a novel hybrid graph representation and learning framework under a multi-task setting, featuring two distinct types of CDFGs derived from two different sources. Furthermore, various models are proposed to fuse features and knowledge in joint, sequential, and parallel learning architectures, aiming to improve the overall accuracy and generalization in predicting QoR and approximating the Pareto frontier (PF). Experimental results show that our framework can attain a higher level of performance than the state-of-the-art baseline models over unseen designs, with an average relative improvement of 47.4 % and 16.0 % for resource utilization and performance metrics, respectively. Additionally, considering various HLS designs with different design space sizes, a 26.8 % enhancement in DSE PF approximation is observed.
引用
收藏
页码:189574 / 189589
页数:16
相关论文
共 50 条
  • [21] A genetic algorithm for the design space exploration of datapaths during high-level synthesis
    Krishnan, Vyas
    Katkoori, Srinivas
    IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2006, 10 (03) : 213 - 229
  • [22] Machine Learning to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration
    Wang, Zi
    Schafer, Benjamin Carrion
    PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2020,
  • [23] Scheduling Information-Guided Efficient High-Level Synthesis Design Space Exploration
    Qian, Xingyue
    Shi, Jian
    Shi, Li
    Zhang, Haoyang
    Bian, Lijian
    Qian, Weikang
    2022 IEEE 40TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2022), 2022, : 203 - 206
  • [24] Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints
    Prost-Boucle, Adrien
    Muller, Olivier
    Rousseau, Frederic
    JOURNAL OF SYSTEMS ARCHITECTURE, 2014, 60 (01) : 79 - 93
  • [25] Area-oriented Iterative Method for Design Space Exploration with High-Level Synthesis
    da Silva, Jeferson Santiago
    Bampi, Sergio
    2015 IEEE 6TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2015,
  • [26] Leveraging Prior Knowledge for Effective Design-Space Exploration in High-Level Synthesis
    Ferretti, Lorenzo
    Kwon, Jihye
    Ansaloni, Giovanni
    Di Guglielmo, Giuseppe
    Carloni, Luca P.
    Pozzi, Laura
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (11) : 3736 - 3747
  • [27] Decomposition based estimation of distribution algorithm for high-level synthesis design space exploration
    Yao, Yuan
    Hong, Huiliang
    Wang, Shanshan
    Xiao, Chenglong
    INTEGRATION-THE VLSI JOURNAL, 2025, 100
  • [28] Parallel High-Level Synthesis Design Space Exploration for Behavioral IPs of Exact Latencies
    Schafer, Benjamin Carrion
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2017, 22 (04)
  • [29] A high-level interconnect power model for design space exploration
    Gupta, P
    Zhong, L
    Jha, NK
    ICCAD-2003: IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2003, : 551 - 558
  • [30] A graph-based framework for High-level test synthesis
    Bashari, Ali Pourghaffari
    Pourmozafari, Saadat
    WORLD CONGRESS ON ENGINEERING 2007, VOLS 1 AND 2, 2007, : 486 - +