A graph-based framework for High-level test synthesis

Improving testability during the early stages of High-level synthesis has several advantages including reduced test hardware overhead and design iterations. Recently, BIST techniques have changed their way from traditional DFT to modern SFT approach. In this paper, we present a novel flexible register allocation method for digital circuits, which is based on considering testability parameters as weights of register compatibility graph and weighted graph maximum clique algorithm in which during the synthesis, testability considerations impact on register allocation.