On-chip crossbar architecture with load-separation scheme

被引:0
|
作者
Zhao, Hongzhi [1 ]
Liu, Xuemin [2 ]
机构
[1] School of Computer and Information Technology, Beijing Jiaotong University, Beijing 100044, China
[2] Computer Network Information Center, Chinese Academy of Sciences, Beijing 100080, China
来源
Journal of Computational Information Systems | 2012年 / 8卷 / 01期
关键词
Crossbar architecture - Load-separation scheme - Maximum works - Network address - Network scale - Network-on-chip - On chips - Separation rate - Traffic pattern;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:387 / 396
相关论文
共 50 条
  • [41] ONE-SIDED BINARY TREE-CROSSBAR SWITCHING FOR ON-CHIP NETWORKS
    Oruc, A. Yavuz
    2015 49TH ANNUAL CONFERENCE ON INFORMATION SCIENCES AND SYSTEMS (CISS), 2015,
  • [42] A simplicial CNN architecture for on-chip image processing
    Mandolesi, PS
    Julian, P
    Andreou, AG
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS, 2004, : 29 - 32
  • [43] A RAM ARCHITECTURE FOR CONCURRENT ACCESS AND ON-CHIP TESTING
    LIU, JC
    SHIN, KG
    IEEE TRANSACTIONS ON COMPUTERS, 1991, 40 (10) : 1153 - 1159
  • [44] Architecture of the on-chip debug module for a multiprocessor system
    Zhang, Kexin
    Yu, Jian
    CIVIL, ARCHITECTURE AND ENVIRONMENTAL ENGINEERING, VOLS 1 AND 2, 2017, : 1505 - 1509
  • [45] An analyzable on-chip network architecture for embedded systems
    Luedtke, Daniel
    Tutsch, Dietmar
    Hommel, Guenter
    EMBEDDED SYSTEMS - MODELING, TECHNOLOGY AND APPLICATIONS, PROCEEDINGS, 2006, : 63 - +
  • [46] A Novel Architecture for On-Chip Path Delay Measurement
    Wang, Xiaoxiao
    Tehranipoor, Mohammad
    Datta, Ramyanshu
    ITC: 2009 INTERNATIONAL TEST CONFERENCE, 2009, : 320 - +
  • [47] The Y architecture for on-chip interconnect: Analysis and methodology
    Chen, HY
    Cheng, CK
    Kahng, AB
    Mandoiu, II
    Wang, QK
    Yao, B
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (04) : 588 - 599
  • [48] Unified On-chip Memory Allocation for SIMT Architecture
    Hayes, Ari B.
    Zhang, Eddy Z.
    PROCEEDINGS OF THE 28TH ACM INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, (ICS'14), 2014, : 293 - 302
  • [49] A complete strategy for testing an on-chip multiprocessor architecture
    Aktouf, C
    IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (01): : 18 - 28
  • [50] Designing High Bandwidth On-Chip Caches Architecture
    Computer Architecture News, 25 (02):