A VLSI architecture evaluation of a syntax element level parallel arithmetic entropy coder for parallel H.264 encoder

被引：0
|
作者：
Chen, Sheng-Gang [1 ]
Chen, Shu-Ming [1 ]
Gu, Hui-Tao [1 ]
Liu, Yao [1 ]
机构：
[1] Computer School, National University of Defense Technology, Changsha, Hunan 410073, China
来源：
Tien Tzu Hsueh Pao/Acta Electronica Sinica | 2012年 / 40卷 / 02期
关键词：
Syntactics;
D O I：
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学科分类号：
摘要：
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页码：400 / 405
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