共 50 条
- [21] A low-power VLSI architecture for intra prediction in H.264 ADVANCES IN INFORMATICS, PROCEEDINGS, 2005, 3746 : 633 - 640
- [22] A Low Power Architecture for H.264 Encoder in Intra Prediction Mode 2014 INTERNATIONAL CONFERENCE ON COMMUNICATIONS AND SIGNAL PROCESSING (ICCSP), 2014,
- [23] Architecture of an HDTV intraframe predictor for a H.264 decoder IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 228 - +
- [24] A New VLSI Architecture Implementation for H.264 Decoder 2009 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLUMES I & II, 2009, : 1057 - 1058
- [25] An efficient intra prediction hardware architecture for H.264 video decoding DSD 2007: 10TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2007, : 448 - 451
- [26] A reconfigurable design on intra prediction decoder engine for H.264/AVC decoding chipset Energy Education Science and Technology Part A: Energy Science and Research, 2014, 32 (06): : 6939 - 6954
- [28] High-Parallel Architecture for H.264/AVC Intra Prediction Implemented via VLSI 2013 IEEE INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY AND IDENTIFICATION (ASID), 2013,
- [30] Intra Prediction Hardware Module For High-Profile H.264/AVC Encoder. SPA 2010: SIGNAL PROCESSING ALGORITHMS, ARCHITECTURES, ARRANGEMENTS, AND APPLICATIONS CONFERENCE PROCEEDINGS, 2010, : 62 - 67