A Novel Technique to Design GNRFET Based Ternary Logic Circuits for High-Performance Applications

Abstract: A two-valued logic design has a large number of nodes and connections, which results in a high delay and high-power dissipation. The ternary logic is an alternate solution to avoid problems with traditional two-valued logic. The ternary logic offers high band width, less interconnection length, lower chip area, more computation, and logical operations. In this paper, the ternary logic complicated schematics such as half- and full-adders are proposed. The proposed half and full adders are developed utilizing futuristic technology i.e., graphene nanoribbon transistor (GNRFET). The remarkable characteristics of GNRFET made it a promising contender for ternary logic circuit designs. The GNRFET threshold voltage (Vth) is obtained by varying graphene nanoribbon (GNR) dimer lines (n). The proposed ternary adders are developed and simulated in HSPICE simulator. The performance like delay, power, power-delay-product (PDP) and energy-delay-product (EDP) are investigated for presented adders. Furthermore, the acquired performance values are compared to conventional carbon nanotube FET (CNTFET) designs. From the study, it is observed that GNRFET ternary adders showed improved delay, PDP and EDP up to 69.46, 87.67 and 88.32% over the existing CNTFET-based designs. While increase in power dissipation of 42.74%. © Pleiades Publishing, Ltd. 2024. ISSN 1063-7397, Russian Microelectronics, 2024, Vol. 53, No. 5, pp. 492–499. Pleiades Publishing, Ltd., 2024.