共 50 条
- [31] A Novel ESD Protection Circuit Applied in High-speed CMOS IC 2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 345 - 348
- [33] A novel technique for full-wave modeling of largescale three-dimensional high-speed on/off-chip interconnect structures 2003 IEEE INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES, 2003, : 39 - 42
- [36] IVEC: Off-Chip Memory Integrity Protection for Both Security and Reliability ISCA 2010: THE 37TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, 2010, : 395 - 406
- [37] Optimizing circuit performance and ESD protection for high-speed differential I/Os PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2007, : 149 - 152
- [38] FinFET SCR Structure Optimization for High-Speed Serial Links ESD Protection 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2016,
- [39] Novel Topological Layout for ESD protection for high-speed I/O applications 2022 INTERNATIONAL EOS/ESD SYMPOSIUM ON DESIGN AND SYSTEM (IEDS), 2022,