共 50 条
- [41] On low-capture-power test generation for scan testing 23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 265 - 270
- [42] Search Space Reduction for Low-Power Test Generation 2013 22ND ASIAN TEST SYMPOSIUM (ATS), 2013, : 171 - 176
- [44] Automatic test pattern generation FORMAL METHODS FOR HARDWARE VERIFICATION, 2006, 3965 : 30 - 55
- [46] A low power test vector seed generation algorithm for SoC 2020 5TH INTERNATIONAL CONFERENCE ON MECHANICAL, CONTROL AND COMPUTER ENGINEERING (ICMCCE 2020), 2020, : 1634 - 1637
- [47] Generation of test sequences with low power dissipation for sequential circuits IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2004, E87D (03): : 530 - 536
- [48] Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, : 530 - 537
- [49] Power-aware Test Pattern Generation for improved concurrency at the core level ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 300 - +
- [50] Design and Implementation of Low Power Test Pattern Generator Using Low Transitions LFSR 2017 INTERNATIONAL CONFERENCE ON COMMUNICATION AND SIGNAL PROCESSING (ICCSP), 2017, : 467 - 471