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- [42] Min/max on-chip inductance models and delay metrics 38TH DESIGN AUTOMATION CONFERENCE PROCEEDINGS 2001, 2001, : 341 - 346
- [43] Layout techniques for minimizing on-chip interconnect self inductance 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 566 - 571
- [44] Bounding bus delay and noise effects of on-chip inductance SIGNAL PROPAGATION ON INTERCONNECTS, PROCEEDINGS, 2004, : 167 - 170
- [45] Analysis of RF flip-chip on-chip inductance with novel measurement technology 53RD ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2003 PROCEEDINGS, 2003, : 1253 - 1257
- [46] Inductance Modeling for On-chip interconnects using Elevated coplanar waveguide 2006 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS, 2006, : 195 - +
- [47] Modeling and characterization of on-chip inductance for high speed VLSI design NSTI NANOTECH 2004, VOL 2, TECHNICAL PROCEEDINGS, 2004, : 80 - 85
- [49] Development of Microwave Kinetic Inductance Detectors for a THz On-Chip Spectrometer Journal of Low Temperature Physics, 2024, 214 : 230 - 237
- [50] On the efficacy of simplified 2D on-chip inductance models 39TH DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2002, 2002, : 757 - 762