Grasping the impact of on-chip inductance

被引:0
|
作者
Massoud, Yehia [1 ]
Ismail, Yehea [1 ]
机构
[1] Northwestern University, United States
来源
IEEE Circuits and Devices Magazine | 2001年 / 17卷 / 04期
关键词
Computer simulation - Finite difference method - Finite element method - Integral equations - Interconnection networks - Maxwell equations - Performance - VLSI circuits;
D O I
10.1109/101.950046
中图分类号
学科分类号
摘要
The rapid advancements in process technology and heightening market pressures for functional integration are resulting in large VLSI chips operating at steadily increasing frequencies. Understanding the effects of on-chip inductance in high-speed integrated circuits will be crucial to high-performance design. This paper briefly discusses the importance, physical nature, effects, and extraction issues of on-chip inductance.
引用
收藏
页码:14 / 21
相关论文
共 50 条
  • [21] On the impact of on-chip inductance on signal nets under the influence of power grid noise
    Chen, T
    DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, : 451 - 457
  • [22] Figures of merit to characterize the importance of on-chip inductance
    Ismail, YI
    Friedman, EG
    Neves, JL
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1999, 7 (04) : 442 - 449
  • [23] Unified Inductance Calculations for On-Chip Planar Spirals
    Xie, Shuangwen
    Fu, Jun
    2022 29TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (IEEE ICECS 2022), 2022,
  • [24] The importance of inductance and inductive coupling for on-chip wiring
    Deutsch, A
    Smith, H
    Katopis, GA
    Becker, WD
    Coteus, PW
    Surovic, CW
    Kopcsay, GV
    Rubin, BJ
    Dunne, RP
    Gallo, T
    Knebel, DR
    Krauter, BL
    Terman, LM
    SaiHalasz, GA
    Restle, PJ
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 1997, : 53 - 56
  • [25] On-chip interconnect inductance - Friend or foe (invited)
    Wong, SS
    Yue, P
    Chang, R
    Kim, SY
    Kleveland, B
    O'Mahony, F
    4TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2003, : 389 - 394
  • [26] High-frequency on-chip inductance model
    Sim, SP
    Lee, K
    Yang, CY
    IEEE ELECTRON DEVICE LETTERS, 2002, 23 (12) : 740 - 742
  • [27] Effects of on-chip inductance on power distribution grid
    Muramatsu, A
    Hashimoto, M
    Onodera, H
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2005, E88A (12) : 3564 - 3572
  • [28] Layout techniques for on-chip interconnect inductance reduction
    Tu, SW
    Jou, JY
    Chang, YW
    ASP-DAC 2004: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, 2004, : 269 - 273
  • [29] Figures of merit to characterize the importance of on-chip inductance
    Ismail, YI
    Friedman, EG
    Neves, JL
    1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 560 - 565
  • [30] Global interconnect optimization in the presence of on-chip inductance
    Roy, Abinash
    Chowdhury, Masud H.
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 885 - 888