Bounding bus delay and noise effects of on-chip inductance

On-chip inductance depends on current return paths and is unreasonably computationally expensive to extract and model in the general case. A practical solution is to provide a well-defined power supply network so the current return paths are more predictable. This paper develops a model of bus delay and noise as a function of the physical dimensions of busses and the switching parameters. It applies this model to develop bounds on the inductive effects on delay and noise for on-chip busses in 180, 130 and 100 nm processes. If one power or ground line is interdigitated with every four bus lines, the RLC noise and delay are no more than 7% greater than RC models would predict. Designers may treat this delay and noise as small penalties for all busses rather than having to individually extract and model inductance on each bus.