Design and measurement of an inductance-oscillator for analyzing on-chip inductance impact on wire delay

A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip wire delay. iOSC is a ling oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip using 0.13-mum node process is fabricated to demonstrate concept of the iOSC. Four wire structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency global signal lines. The structure with largest inductance variation measured 99 ps delay difference while newly proposing twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. This experiment also provides designers with a guideline for ground density from inductance standpoint. iOSC confirms that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing in high-speed LSI designs.