Inductance Modeling for On-chip interconnects using Elevated coplanar waveguide

As technology advances into the very deep submicron era, the operating frequencies are fast reaching the vicinity of several gigahertz and switching times are getting to the sub nanosecond levels. The ever increasing quest for high speed applications highlighted the previously negligible inductive effects of interconnects, such as signal delay, over shoot, and crosstalk[1]. At gigahertz frequencies, long interconnect wires exhibit transmission line behavior[8]. This paper describes the inductive effects of on-chip interconnects using elevated coplanar waveguide structure as a transmission line for multilayer chip. It uses realistic test structures that study the inductive effect of local interconnects to typical power and ground grids. Electrical equivalent modeling for ECPW was derived using complex image method. ECPW structure was designed for 10GHz and simulated in Ansoft HFSS V9.2.1. ECPW structure shows an insertion loss of 0.02 dB and return loss of -23 dB. Also shows the inductive reactance dominates the resistance at higher frequencies.