Hardware-oriented rate control algorithm for JPEG2000 and its VLSI architecture design

For the purpose of decreasing the quantity of operation and reducing the size of memory, a new rate control algorithm for JPEG2000 is proposed utilizing the rate pre-allocation method, the VLSI architecture design of which is given as well. After wavelet transform and quantification on the original image, a prediction module is introduced to estimate the entropy of the EBCOT code block within the available bit-plane, and then the proportion between the estimate entropy of each code block and the summation estimate entropy of all code blocks is used to allocate the rate for each code block. EBCOT coder truncates the code stream according to the allocated rate, and thus the operation time consumed by the T1 coder is reduced. After coded by the T1 coder, each code block can be packed to the output, with no need for computing the rate-distortion slope and completing the rate-distortion optimization truncation. Experimental results show that the proposed algorithm can efficiently reduce the cost of computation and memory usage, and that it is most suitable for hardware implementation.