Design and Implementation of VLSI for Finite State Entropy Encoding

被引：0

作者：

Huang, Hai ^{[1
]}

Xing, Lin ^{[2
]}

Na, Ning ^{[2
]}

Zhang, Guoliang ^{[3
]}

Zhao, Shilei ^{[1
]}

Liu, Zhiwei ^{[1
]}

机构：

[1] School of Software and Microelectronics, Harbin University of Science and Technology, Harbin,150080, China

[2] School of Computer Science and Technology, Harbin University of Science and Technology, Harbin,150080, China

[3] Ninth Research Institute, China Aerospace Science and Technology Corporation, Beijing,100094, China

来源：

Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao/Journal of Computer-Aided Design and Computer Graphics | 2021年 / 33卷 / 04期

关键词：

D O I：

10.3724/SP.J.1089.2021.18575

中图分类号：

学科分类号：

摘要：

The Zstd (Zstandard) lossless compression algorithm that implemented by software is difficult to meet the de-mand of compression speed in specific application field when processing massive data. It is an effective solution to this problem by using the hardware acceleration scheme, especially for the hardware acceleration of FSE (fi-nite state entropy). Thus, a hardware implementation of the compression and decompression in FSE is proposed for Zstd. This scheme determines the optimal hardware acceleration step by fixing the size of compression table, reduces the storage space and improves the transmission speed by adding hardware modules of sequence map-ping, enhances the time of parallel processing by dividing the seven-stages of flow and realizes the architecture by software and hardware collaboration. The proposed architecture is implemented in the TSMC 55 nm process, and the highest frequency can reach 750 MHz. The experimental results show that compared with the software implementation, the speed of the whole compression is more than 9 times faster, the speed of the whole decompression is more than the 100 times faster. © 2021, Beijing China Science Journal Publishing Co. Ltd. All right reserved.

引用

页码：640 / 648

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