Device level 3D integration technologies for high performance/reliability modules

被引:0
|
作者
Houston, Paul [1 ]
Lewis, Brian [1 ]
Pathammavong, Keck [1 ]
Sparks, Tim [1 ]
Baldwin, Daniel F. [1 ]
机构
[1] ENGENT, Inc., Enabling Next Generation Technologies, 3140 Northwoods Parkway, Norcross, GA 30071, United States
来源
Advancing Microelectronics | 2010年 / 37卷 / 06期
关键词
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:12 / 18
相关论文
共 50 条
  • [21] System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform
    Agrawal, Prashant
    Milojevic, Dragomir
    Raghavan, Praveen
    Catthoor, Francky
    Van der Perre, Liesbet
    Beyne, Eric
    Varadarajan, Ravi
    IEEE EMBEDDED SYSTEMS LETTERS, 2014, 6 (04) : 85 - 88
  • [22] Chip to Wafer Direct Bonding Technologies for High Density 3D Integration
    Sanchez, L.
    Bally, L.
    Montmayeul, B.
    Fournel, F.
    Dafonseca, J.
    Augendre, E.
    Di Cioccio, L.
    Carron, V.
    Signamarcheix, T.
    Taibi, R.
    Mermoz, S.
    Lecarpentier, G.
    2012 IEEE 62ND ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2012, : 1960 - 1964
  • [23] High Reliability Insert-Bump Bonding Process for 3D Integration
    Song, Jun-Yeob
    Lee, Jae Hak
    Kim, Hyoung Joon
    Lee, Chang Woo
    Ha, Tae Ho
    2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [24] Wafer and Die Bonding Technologies for 3D Integration
    Farrens, Shari
    MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION, 2009, 1112 : 55 - 65
  • [25] 3D Integration Technologies for MEMS/IC Systems
    Ramm, Peter
    Klumpp, Armin
    Weber, Josef
    PROCEEDINGS OF THE 2009 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2009, : 138 - 141
  • [26] The Development of Wafer-Level 3D High-Density Junction Capacitor for Passive Device Integration in SiP
    Wang, Huijuan
    Yu, Daquan
    He, Ran
    Cao, Liqiang
    Du, Tianmin
    Wan, Lixi
    2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
  • [27] Advanced Device Performance Impact by Wafer Level 3D Stacked Architecture
    Liu, J. C.
    Huang, K. C.
    Chu, Y. H.
    Hung, J. M.
    Change, C. C.
    Wei, Y. L.
    Lin, J. S.
    Kao, M. F.
    Chen, P. T.
    Huang, S. Y.
    Lin, H. C.
    Wang, W. D.
    Chou, Peter
    Lu, C. F.
    Tu, Y. L.
    Shiu, F. J.
    Huang, C. F.
    Lin, C. H.
    Lu, T. H.
    Yaung, D. N.
    2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2015,
  • [28] 3D high performance packaging of electronic equipments and guaranteed reliability
    Research Lab. TSUKUI, 3-4-1, 6-401 Minamigaoka, Hadano-shi, Kanagawa 257-0013, Japan
    J. Jpn. Inst. Electron. Packag., 2008, 5 (317-325):
  • [29] 3D Copper TSV Integration, Testing and Reliability
    Farooq, M. G.
    Graves-Abe, T. L.
    Landers, W. F.
    Kothandaraman, C.
    Himmel, B. A.
    Andry, P. S.
    Tsang, C. K.
    Sprogis, E.
    Volant, R. P.
    Petrarca, K. S.
    Winstel, K. R.
    Safran, J. M.
    Sullivan, T. D.
    Chen, F.
    Shapiro, M. J.
    Hannon, R.
    Liptak, R.
    Berger, D.
    Iyer, S. S.
    2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM), 2011,
  • [30] Challenges in the Reliability of 3D Integration using TSVs
    Stiebing, M.
    Vogel, D.
    Steller, W.
    Wolf, M. J.
    Wunderle, B.
    2015 16TH INTERNATIONAL CONFERENCE ON THERMAL, MECHANICAL AND MULTI-PHYSICS SIMULATION AND EXPERIMENTS IN MICROELECTRONICS AND MICROSYSTEMS (EUROSIME), 2015,