New statistical method for maximum power estimation in CMOS VLSI circuits

被引:0
|
作者
Evmorfopoulos, N.E. [1 ]
Avaritsiotis, J.N. [1 ]
机构
[1] Dept. of Elec. and Comp. Engineering, Natl. Technical University of Athens, 9, Iroon Polytechniou St., Zographou, Athens, 15773, Greece
关键词
D O I
10.1155/2000/39526
中图分类号
学科分类号
摘要
引用
收藏
页码:215 / 233
相关论文
共 50 条
  • [41] POWER-CONSUMPTION ESTIMATION IN CMOS VLSI CHIPS
    LIU, D
    SVENSSON, C
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (06) : 663 - 670
  • [42] Efficient algorithms for multilevel power estimation of VLSI circuits
    Bachmann, WW
    Huss, SA
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2005, 13 (02) : 238 - 254
  • [43] A precise model for leakage power estimation in VLSI circuits
    Derakhshandeh, J
    Masoumi, N
    Kasiri, B
    Farazmand, Y
    Akbarzadeh
    Aghnoot, S
    FIFTH INTERNATIONAL WORKSHOP ON SYSTEM-ON-CHIP FOR REAL-TIME APPLICATIONS, PROCEEDINGS, 2005, : 337 - 340
  • [44] Maximal power estimation for CMOS VLSI circuit design
    Chen, WJ
    Fang, SC
    JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS, 1999, 22 (02) : 251 - 257
  • [45] Maximal power estimation for CMOS VLSI circuit design
    Chen, Wang-Jin
    Fang, Sung-Chang
    Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, 1999, 22 (02): : 251 - 257
  • [46] GA-BASED MAXIMUM POWER DISSIPATION ESTIMATION OF VLSI SEQUENTIAL CIRCUITS OF ARBITRARY DELAY MODELS
    Lu Junming Lin Zhcnghui (LSI Research Institute
    Journal of Electronics(China), 2002, (04) : 378 - 386
  • [47] Fast transient power and noise estimation for VLSI circuits
    Eisenmann, Wolfgang T.
    Graeb, Helmut E.
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994, : 252 - 257
  • [48] Statistical Leakage Estimation of Bounds on Nanometric CMOS Circuits
    Mendoza Vazquez, Raymundo
    DTIS: 2009 4TH IEEE INTERNATIONAL CONFERENCE ON DESIGN & TECHNOLOGY OF INTEGRATED SYSTEMS IN NANOSCALE ERA, PROCEEDINGS, 2009, : 58 - 63
  • [49] A new statistical approach to timing analysis of VLSI circuits
    Lin, RB
    Wu, MC
    ELEVENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1997, : 507 - 513
  • [50] Estimation of maximum power for CMOS combinational circuits using tabu-hierarchy genetic algorithm
    Zhang, XL
    Yu, JB
    Li, SY
    2002 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS AND WEST SINO EXPOSITION PROCEEDINGS, VOLS 1-4, 2002, : 1161 - 1164