Maximal power estimation for CMOS VLSI circuit design

被引：0

作者：

Chen, WJ ^{[1
]}

Fang, SC

机构：

[1] Kao Yuan Inst Technol, Dept Elect Engn, Kaohsiung 804, Taiwan

[2] Womens Coll Arts & Technol, Dept Accounting, Tainan 710, Taiwan

来源：

JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS | 1999年 / 22卷 / 02期

关键词：

power consumption; maximum power; simulated annealing;

D O I：

10.1080/02533839.1999.9670462

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

In this paper we propose a simulation-based algorithm, which is developed using the simulated annealing algorithm, to estimate the maximal power dissipation of sequential and combinational circuits. To trade off between the execution time and the outcomes, we use three strategies with different search spaces to generate input patterns. A statistical model is employed to analyze the equilibrium condition for each temperature in our simulated annealing process. The glitch phenomena caused by the gate delay and signal transition are also considered in this paper.

引用

页码：251 / 257

页数：7

共 50 条

[1] Maximal power estimation for CMOS VLSI circuit design
Chen, Wang-Jin
Fang, Sung-Chang
Journal of the Chinese Institute of Engineers, Transactions of the Chinese Institute of Engineers,Series A/Chung-kuo Kung Ch'eng Hsuch K'an, 1999, 22 (02): : 251 - 257
[2] Estimation of maximum power in CMOS VLSI circuit
Li, F
Zhao, WQ
Tang, PS
PROCEEDINGS OF THE 6TH INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN & COMPUTER GRAPHICS, 1999, : 375 - 379
[3] Low power VLSI CMOS circuit design
Elmasry, MI
ICM 2000: PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2000, : 4 - 4
[4] Design Methodologies and Circuit Optimization Techniques for Low Power CMOS VLSI Design
Geetha, B. T.
Padmavathi, B.
Perumal, V
2017 IEEE INTERNATIONAL CONFERENCE ON POWER, CONTROL, SIGNALS AND INSTRUMENTATION ENGINEERING (ICPCSI), 2017, : 1759 - 1763
[5] Pattern-based maximal power estimation for VLSI chip design
Chen, WJ
Feng, WS
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1997, E80A (11) : 2300 - 2307
[6] Pattern-based maximal power estimation for VLSI chip design
Natl Taiwan Univ, Taipei, Taiwan
IEICE Trans Fund Electron Commun Comput Sci, 11 (2300-2307):
[7] A low-power correlation-derivative CMOS VLSI circuit for bearing estimation
Julián, P
Andreou, AG
Goldberg, DH
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2006, 14 (02) : 207 - 212
[8] AN UNDERGRADUATE VLSI CMOS CIRCUIT-DESIGN LABORATORY
WILLIAMS, RW
IEEE TRANSACTIONS ON EDUCATION, 1991, 34 (01) : 47 - 51
[9] VLSI scaling methods and low power CMOS buffer circuit
Vijay Kumar Sharma
Manisha Pattanaik
Journal of Semiconductors, 2013, 34 (09) : 96 - 103
[10] VLSI scaling methods and low power CMOS buffer circuit
Vijay Kumar Sharma
Manisha Pattanaik
Journal of Semiconductors, 2013, (09) : 96 - 103

← 1 2 3 4 5 →