Maximal power estimation for CMOS VLSI circuit design

被引：0
|
作者：
Chen, WJ [1 ]
Fang, SC
机构：
[1] Kao Yuan Inst Technol, Dept Elect Engn, Kaohsiung 804, Taiwan
[2] Womens Coll Arts & Technol, Dept Accounting, Tainan 710, Taiwan
来源：
JOURNAL OF THE CHINESE INSTITUTE OF ENGINEERS | 1999年 / 22卷 / 02期
关键词：
power consumption; maximum power; simulated annealing;
D O I：
10.1080/02533839.1999.9670462
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
In this paper we propose a simulation-based algorithm, which is developed using the simulated annealing algorithm, to estimate the maximal power dissipation of sequential and combinational circuits. To trade off between the execution time and the outcomes, we use three strategies with different search spaces to generate input patterns. A statistical model is employed to analyze the equilibrium condition for each temperature in our simulated annealing process. The glitch phenomena caused by the gate delay and signal transition are also considered in this paper.
引用
收藏
页码：251 / 257
页数：7
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