Novel design of reversible full adder with optimal delay

被引:0
|
作者
Li, Ming-Cui [1 ]
Zhou, Ri-Gui [1 ]
Li, Hai-Sheng [1 ]
机构
[1] School of Information Engineering, East China Jiaotong University, No. 808, Shuanggang East Street, Nanchang 330013, China
来源
ICIC Express Letters | 2014年 / 8卷 / 09期
关键词
14;
D O I
暂无
中图分类号
学科分类号
摘要
引用
收藏
页码:2551 / 2558
相关论文
共 50 条
  • [1] Design of a Novel Reversible Full Adder and Reversible Full Subtractor
    AnanthaLakshmi, A. V.
    Sudha, G. F.
    ADVANCES IN COMPUTING AND INFORMATION TECHNOLOGY, VOL 3, 2013, 178 : 623 - 632
  • [2] A NOVEL REVERSIBLE MULTILAYER FULL ADDER CIRCUIT DESIGN IN QCA TECHNOLOGY
    Faraji, Reza
    Rezai, Abdalhossein
    FACTA UNIVERSITATIS-SERIES ELECTRONICS AND ENERGETICS, 2024, 37 (03) : 437 - 453
  • [3] Novel Quaternary Quantum Reversible Half Adder and Full Adder Circuits
    Doshanlou, Abdollah Norouzi
    Haghparast, Majid
    Hosseinzadeh, Mehdi
    IETE JOURNAL OF RESEARCH, 2022, 68 (02) : 1525 - 1531
  • [4] Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions
    Praghash, K.
    Metha, S. Arun
    Tanuja, B. Sai
    Preethi, K.
    Chandana, N. P. N. S.
    WIRELESS PERSONAL COMMUNICATIONS, 2022, 126 (04) : 3041 - 3069
  • [5] Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions
    K. Praghash
    S. Arun Metha
    B. Sai Tanuja
    K. Preethi
    N. P. N. S. Chandana
    Wireless Personal Communications, 2022, 126 : 3041 - 3069
  • [6] Design of a reversible ALU using a novel coplanar reversible full adder and MF gate in QCA nanotechnology
    Ramin Aliabadian
    Mehdi Golsorkhtabaramiri
    Saeed Rasouli Heikalabad
    Mohammad Karim Sohrabi
    Optical and Quantum Electronics, 2023, 55
  • [7] Design of a reversible ALU using a novel coplanar reversible full adder and MF gate in QCA nanotechnology
    Aliabadian, Ramin
    Golsorkhtabaramiri, Mehdi
    Heikalabad, Saeed Rasouli
    Sohrabi, Mohammad Karim
    OPTICAL AND QUANTUM ELECTRONICS, 2023, 55 (02)
  • [8] Design of a New Parity Preserving Reversible Full Adder
    Haghparast, Majid
    Shoaei, Soghra
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2015, 24 (01)
  • [9] Verilog Design of Full Adder Based on Reversible Gates
    Singh, Varun Pratap
    Rai, Manish
    2016 2ND INTERNATIONAL CONFERENCE ON ADVANCES IN COMPUTING, COMMUNICATION, & AUTOMATION (ICACCA) (FALL), 2016, : 65 - 69
  • [10] A Novel Design of Area Efficient Full Adder Architecture using Reversible Logic Gates
    Ganesh, Chokkakula
    Kumar, Aruru Sai
    Santhosh, P.
    Ramya, Anreddy
    Kumar, Chennoji Shiva
    Thivani, Ponugoti
    2024 7TH INTERNATIONAL CONFERENCE ON DEVICES, CIRCUITS AND SYSTEMS, ICDCS 2024, 2024, : 107 - 111