Hybrid approach of filtering unnecessary way accesses for set-associative caches

Power has been a big issue in processor design for several years. Conventional popular approaches for addressing this issue like DVFS (Dynamic Voltage Frequency Scaling) now hit the law of diminishing returns. As multi/many-core processors becoming the main stream processors, caches account for more and more CPU die area and power, this paper presents using filtering unnecessary way accesses to reduce dynamic power consumption of caches shared by instruction and data. The methods include using Invalid Filter, which could eliminate accesses to cache ways contained invalid blocks, and I/D Filter, which could eliminate accesses to cache ways contained instruction/data access type mismatch blocks, and Tag-2 Filter, which could eliminate accesses to cache ways contained tag lowest 2 bits mismatch blocks. Since the methods reducing the activities happened in cache architecture, dynamical CPU power could be significantly decreased. In the paper, we also propose combining the above methods together, which is called Invalid+I/D+Tag-2 Filter, in an attempt to achieve better power saving results. We have verified the effectiveness and complementariness of the three proposed methods through analysis and experiments. Also, our evaluations show that, we could obtain 19.6%~47.8% (which is on average 34.3%) improvement on a 64KB-4way set-associative cache and 19.6%~55.2% (which is on average 39.2%) improvement on a 128KB-8way set-associative cache comparing to Invalid+I/D Filter, and 16.1%~27.7% (which is on average 16.6%) improvement on a 64KB-4way set-associative cache and 6.9%~44.4% (which is on average 25.0%) improvement on a 128KB-8way set-associative cache comparing to Invalid+Tag-2 Filter, respectively.