Voltage Skew-Based Test Technique for Pre-Bond TSVs in 3-D ICs

被引:0
|
作者
Liu, Jun [1 ,2 ]
Chen, Zhi [1 ,2 ]
Chen, Tian [1 ,2 ]
Wu, Xi [1 ,2 ]
Liang, Huaguo [3 ]
Yuan, Xiaohui [4 ]
机构
[1] Hefei Univ Technol, Sch Comp & Informat, Anhui Prov Key Lab Affect Comp & Adv Intelligent M, Hefei 230601, Peoples R China
[2] Hefei Univ Technol, Intelligent Interconnected Syst Lab Anhui Prov, Hefei 230601, Peoples R China
[3] HeFei Univ Technol, Sch Microelect, Hefei 230601, Peoples R China
[4] Univ North Texas, Dept Comp Sci & Engn, Denton, TX 76203 USA
基金
中国国家自然科学基金;
关键词
3-D ICs; through silicon via (TSV); resistive open fault; leakage fault; pre-bond TSV test; voltage skew; MODEL;
D O I
10.1109/TCSII.2024.3373897
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In 3D ICs, the manufacturing process of through silicon via (TSV) is still immature, which can result in resistive open faults and leakage faults. Pre-bond TSV tests can effectively improve the performance and yield of 3D ICs. In this brief, a new pre-bond TSV test method based on the voltage skew is proposed. The proposed method charges a pre-set load capacitor during the voltage skew between faulty and fault-free TSV. It then measures the charge time to detect TSV faults. Furthermore, a variable drive inverter is designed to change the duration of voltage skew and recharge the load capacitor. By comparing the twice charge time, the type of TSV faults can be identified. The experimental results show that the proposed method can detect resistive open faults with R-open >= 400 Omega and leakage faults with R-leak >= 20M Omega. Compared to other test methods, the proposed method has higher detection capability.
引用
收藏
页码:3930 / 3934
页数:5
相关论文
共 50 条
  • [1] Pre-Bond Probing of TSVs in 3D Stacked ICs
    Noia, Brandon
    Chakrabarty, Krishnendu
    [J]. 2011 IEEE INTERNATIONAL TEST CONFERENCE (ITC), 2011,
  • [2] Identification of Defective TSVs in Pre-Bond Testing of 3D ICs
    Noia, Brandon
    Chakrabarty, Krishnendu
    [J]. 2011 20TH ASIAN TEST SYMPOSIUM (ATS), 2011, : 187 - 194
  • [3] Test Cost Optimization Technique for the Pre-Bond Test of 3D ICs
    Chen, Yong-Xiao
    Huang, Yu-Jen
    Li, Jin-Fu
    [J]. 2012 IEEE 30TH VLSI TEST SYMPOSIUM (VTS), 2012, : 102 - 107
  • [4] A BIST Method for TSVs Pre-Bond Test
    Zimouche, Hakim
    Di Natale, Giorgio
    Flottes, Marie-lise
    Rouzeyre, Bruno
    [J]. 2013 8TH INTERNATIONAL DESIGN AND TEST SYMPOSIUM (IDT), 2013,
  • [5] Faulty TSVs Identification and Recovery in 3D Stacked ICs During Pre-bond Testing
    Royl, Surajit Kumar
    Chatterjee, Sobitri
    Giri, Chandan
    Rahaman, Hafizur
    [J]. 2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC), 2013,
  • [6] A 3D IC BIST for pre-bond test of TSVs using Ring Oscillators
    Fkih, Yassine
    Vivet, Pascal
    Rouzeyre, Bruno
    Flottes, Marie-Lise
    Di Natale, Giorgio
    [J]. 2013 IEEE 11TH INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), 2013,
  • [7] Pre-Bond Probing of Through-Silicon Vias in 3-D Stacked ICs
    Noia, Brandon
    Chakrabarty, Krishnendu
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2013, 32 (04) : 547 - 558
  • [8] Vernier ring based pre-bond through silicon vias test in 3D ICs
    Ni, Tianming
    Nie, Mu
    Liang, Huaguo
    Bian, Jingchang
    Xu, Xiumin
    Fang, Xiangsheng
    Huang, Zhengfeng
    Wen, Xiaoqing
    [J]. IEICE ELECTRONICS EXPRESS, 2017, 14 (18):
  • [9] Faulty TSVs Identification in 3D IC Using Pre-bond Testing
    Maity, Dilip Kumar
    Roy, Surajit Kumar
    Giri, Chandan
    [J]. VLSI DESIGN AND TEST, 2017, 711 : 805 - 812
  • [10] Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
    Zhao, Xin
    Lewis, Dean L.
    Lee, Hsien-Hsin S.
    Lim, Sung Kyu
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2011, 30 (05) : 732 - 745