Faulty TSVs Identification in 3D IC Using Pre-bond Testing

被引：0

作者：

Maity, Dilip Kumar ^{[1
]}

Roy, Surajit Kumar ^{[2
]}

Giri, Chandan ^{[2
]}

机构：

[1] Acad Technol, Dept Comp Sci & Engn, Hooghly 712121, India

[2] IIEST, Dept Informat Technol, Sibpur 711103, Howrah, India

来源：

VLSI DESIGN AND TEST | 2017年 / 711卷

关键词：

3D IC; Pre-bond testing; TSV test;

D O I：

10.1007/978-981-10-7470-7_75

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Through-silicon via (TSV) based three-dimensional integrated circuit (3D IC) is gaining remarkable attention in semiconductor industry. The design of 3D IC goes through a complex manufacturing process and testing of TSVs is a critical issue to the researchers. This paper presents an efficient solution for pre-bond TSV testing. The proposed method generates the sequence of test sessions for identifying defective TSVs in a TSV network in reduced test time. Simulation results show the effectiveness of proposed method in terms of test time reduction than the prior works.

引用

页码：805 / 812

页数：8

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