Identification of Faulty TSVs in 3D IC during Pre-bond Testing

被引：3
|
作者：
Maity, Dilip Kumar [1 ]
Roy, Surajit Kumar [2 ]
Giri, Chandan [2 ]
机构：
[1] Acad Technol, Dept Comp Sci & Engn, Hooghly 712121, India
[2] Indian Inst Engn Sci & Technol, Dept Informat Technol, Sibpur 711103, Howrah, India
来源：
2018 31ST INTERNATIONAL CONFERENCE ON VLSI DESIGN AND 2018 17TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS (VLSID & ES) | 2018年
关键词：
3D IC; Pre-bond testing; TSV test;
D O I：
10.1109/VLSID.2018.46
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
Manufacturing of three-dimensional (3D) integrated circuit (IC) using through-silicon vias (TSVs) passes through a complex process and testing of TSVs is a critical issue to the researchers. Pre-bond testing eliminates bad dies before bonding. In this paper, we propose a heuristic approach for pre-bond TSV testing which reduces the test time considerably. The proposed method uses recursive bi-partitioning and padding of test sessions and runs in linear time.
引用
收藏
页码：109 / 114
页数：6
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