Combining Built-In Redundancy Analysis with ECC for Memory Testing

Error Correction Codes (ECC) in current designs typically serve two purposes. For emerging non-volatile memory types (NVM), such as embedded magnetoresistive random access memory (eMRAM), ECC is necessary to counter the probabilistic behavior of the NVM, rendering the combined NVM/ECC a deterministic memory again. The second and much more prominent usage of ECC today is to protect the system against transient faults in the memory, here typically for SRAMs. On the other hand, new defect types for such emerging memories and new technology nodes may exceed reasonable costs of conventional row and column repair. To improve yield, users explore ECC as an option to augment the repair capability of the memory. This paper brings such an augmentation into a standard memory test and repair flow. It allows a user-defined, post silicon trade-off of using all or parts of the corrective power of the ECC for yield improvements and/or for system protection. Experimental results underline the very low area cost of this augmentation.