Forksheet Field-Effect Transistors for Area Scaling and Gate-Drain Capacitance Reduction in Nanosheet-based CMOS Technologies

Nanosheet-based field-effect transistors with dielectric walls between adjacent devices, referred to as forksheet transistors, can improve CMOS scaling by means of (1) space reduction between transistors and (2) gate-drain capacitance reduction. We demonstrate forksheet device fabrication, including self-aligned gate cut formation for lateral channel-channel spaces as small as 12nm. In addition, we discuss pros and cons of different forksheet wall configurations. Dielectric walls positioned at standard cell outer bounds instead of inner bounds have the benefit that wall width scalability is independent of N-P patterning requirements. Source-drain cut patterning is an option to address process-induced wall loss between source-drains.