共 50 条
- [31] An effective modeling of power consumption and time delay for SRAM compiler Journal of Information and Computational Science, 2015, 12 (09): : 3373 - 3382
- [34] An efficient approach to modeling and analysis of power electronic circuits APEC '98 - THIRTEENTH ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, VOLS 1 AND 2, 1998, : 344 - 349
- [36] Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits INTEGRATED CIRCUIT AND SYSTEMS DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2009, 5349 : 21 - +
- [40] Modeling and analysis of path delay faults in VLSI circuits: A statistical approach ICECS 2003: PROCEEDINGS OF THE 2003 10TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2003, : 587 - 590