Deep Learning Approach for Modeling the Power Consumption and Delay of Logic Circuits Employing GNRFET Technology

被引:1
|
作者
Emir, Recep [1 ]
Yamacli, Dilek Surekci [2 ]
Yamacli, Serhan [3 ]
Tekin, Sezai Alper [4 ]
机构
[1] Erciyes Univ, Dept Elect & Elect Engn, TR-38039 Kayseri, Turkiye
[2] Izmir Democracy Univ, Dept Econ, TR-35140 Izmir, Turkiye
[3] Izmir Democracy Univ, Dept Biomed Engn, TR-35140 Izmir, Turkiye
[4] Erciyes Univ, Dept Ind Design Engn, TR-38280 Kayseri, Turkiye
关键词
GNRFET; logic design; deep learning; power consumption; delay; DESIGN; ADDER;
D O I
10.3390/electronics13152993
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The interest in alternative logic technologies is continuously increasing for short nanometer designs. From this viewpoint, logic gates, full adder and D-latch designs based on graphene nanoribbon field effect transistors (GNRFETs) at 7 nm technology nodes were presented, considering that these structures are core elements for digital integrated circuits. Firstly, NOT, NOR and NAND gates were implemented using GNRFETs. Then, 28T full adder and 18T D-latch circuits based on CMOS logic were designed using GNRFETs. As the first result of this work, it was shown through HSPICE simulations that the average power consumption of the considered logic circuits employing GNRFETs was 78.6% lower than those built using classical Si-based MOSFETs. Similarly, the delay advantage of the logic circuits employing GNRFETs was calculated to be 53.2% lower than those using Si-based MOSFET counterparts. In addition, a deep learning model was developed to model both the power consumption and the propagation delay of GNRFET-based logic inverters. As the second result, it was demonstrated that the developed deep learning model could accurately represent the power consumption and delay of GNRFET-based logic circuits with the coefficient of determination (R2) values in the range of 0.86 and 0.99.
引用
收藏
页数:14
相关论文
共 50 条
  • [41] Reliable and ultra-low power approach for designing of logic circuits
    Shams Ul Haq
    Vijay Kumar Sharma
    Analog Integrated Circuits and Signal Processing, 2024, 119 : 85 - 95
  • [42] An approach to reducing power consumption during delay test application
    Li, XW
    Li, HW
    Luo, ZY
    Min, YG
    2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 620 - 623
  • [43] Logic restructuring for delay balancing in wave-pipelined circuits: an integer programming approach
    Sethupathy, S
    Park, N
    Paprzycki, M
    SEVENTH INTERNATIONAL SYMPOSIUM ON SYMBOLIC AND NUMERIC ALGORITHMS FOR SCIENTIFIC COMPUTING, PROCEEDINGS, 2005, : 182 - 188
  • [44] Adaptive Resource Allocation Considering Power-Consumption Outage: A Deep Reinforcement Learning Approach
    Luo, Jia
    Chen, Qianbin
    Tang, Lun
    Zhang, Zhicai
    Li, Yu
    IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, 2023, 72 (06) : 8111 - 8116
  • [45] Modeling the fluctuations of groundwater level by employing ensemble deep learning techniques
    Afan, Haitham Abdulmohsin
    Osman, Ahmedbahaaaldin Ibrahem Ahmed
    Essam, Yusuf
    Ahmed, Ali Najah
    Huang, Yuk Feng
    Kisi, Ozgur
    Sherif, Mohsen
    Sefelnasr, Ahmed
    Chau, Kwok-wing
    El-Shafie, Ahmed
    ENGINEERING APPLICATIONS OF COMPUTATIONAL FLUID MECHANICS, 2021, 15 (01) : 1420 - 1439
  • [46] Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology
    Elangovan, M.
    Sharma, Kulbhushan
    Mahmoud, Haitham A.
    Sachdeva, Ashish
    Jegatheeswaran, S.
    AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, 2024, 177
  • [47] A granular deep learning approach for predicting energy consumption
    Jana, Rabin K.
    Ghosh, Indranil
    Sanyal, Manas K.
    APPLIED SOFT COMPUTING, 2020, 89
  • [48] Monthly Energy Consumption Forecast: A Deep Learning Approach
    Berriel, Rodrigo F.
    Lopes, Andre Texeira
    Rodrigues, Alexandre
    Varejao, Flavio Miguel
    Oliveira-Santos, Thiago
    2017 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN), 2017, : 4283 - 4290
  • [49] DVTS APPROACH TO DIGITAL CMOS CIRCUITS FOR DECREASING TOTAL POWER CONSUMPTION
    Archanadevi, C.
    Prabhu, V.
    2013 INTERNATIONAL CONFERENCE ON INFORMATION COMMUNICATION AND EMBEDDED SYSTEMS (ICICES), 2013, : 1203 - 1207
  • [50] Deep learning-based energy efficiency and power consumption modeling for optical massive MIMO systems
    Salama, Wessam M. M.
    Aly, Moustafa H. H.
    Amer, Eman S. S.
    OPTICAL AND QUANTUM ELECTRONICS, 2023, 55 (06)