Modeling and analysis of path delay faults in VLSI circuits: A statistical approach

With the increased densities of integrated circuits, several different types of faults can occur. Faults in digital circuits resulting from random defects can introduce DC (stuck-at) faults as well as AC (delay) faults. Previous work in statistical modeling and analysis for delay fault testing generally assumes that at most a single delay fault can occur along any given path in the circuit under test [1-3]. In this paper we investigate the statistical effect of multiple delay faults along any path in a circuit under test, and predict the path delay fault probabilities as well as the maximum number of path delay faults for both combinational and sequential benchmark circuits. We begin with the development of a statistical model for path delay faults in VLSI circuits [4], which takes into account multiple delay faults along any signal path.