Integration and verification case of IP-core based system on chip design

被引:2
|
作者
胡越黎 [1 ,2 ]
周谌 [2 ]
机构
[1] School of Mechanical and Electronic Engineering and Automation,Shanghai University
[2] Key Laboratory of Advanced Display and System
关键词
D O I
暂无
中图分类号
TN47 [大规模集成电路、超大规模集成电路];
学科分类号
摘要
In this paper, the design and verification process of an automobile-engine-fan control system on chip (SoC) are introduced. The SoC system, SHU-MV08, reuses four new intellectual property (IP) cores and the design flow is accomplished with 0.35 μm chartered CMOS technology. Some special functions of IP cores, the detailed integration scheme of four IP cores, and the verification method of the entire SoC are presented. To settle the verification problems brought by analog IP cores, NanoSim based chip-level mixed-signal verification method is introduced. The verification time is greatly reduced and the first tape-out achieves success which proves the validity of our design.
引用
收藏
页码:349 / 353
页数:5
相关论文
共 50 条
  • [1] Integration and verification case of IP-core based system on chip design
    胡越黎
    周谌
    Advances in Manufacturing, 2010, (05) : 349 - 353
  • [2] Verification of IP-Core based SoC's
    Deshpande, Anil
    ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 433 - 436
  • [3] A fast IP-core integration methodology for SoC design
    de Oliveira, JA
    de Lima, ME
    Maciel, PR
    Moura, J
    Celso, B
    16TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, SBCCI 2003, PROCEEDINGS, 2003, : 131 - 136
  • [4] Petri net based interface analysis for fast IP-core integration
    de Oliveira, JA
    de Lima, ME
    Maciel, PR
    FIRST ACM AND IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2003, : 34 - 42
  • [5] Improved wrapper cell design for IP-core test
    Yi Qi Yi Biao Xue Bao, 2007, SUPPL. 5 (187-190):
  • [6] Online and off line BIST in IP-core design
    Benso, A
    Chiusano, S
    Di Natale, G
    Prinetto, P
    Bodoni, ML
    IEEE DESIGN & TEST OF COMPUTERS, 2001, 18 (05): : 92 - 99
  • [7] Formal Property Verification of a Remote Memory Access Protocol IP-Core
    Borchers, Kai
    Firchau, Thomas
    2022 IEEE AEROSPACE CONFERENCE (AERO), 2022,
  • [8] Core design and system-on-a-chip integration
    Rincon, AM
    Cherichetti, C
    Monzel, JA
    Stauffer, DR
    Trick, MT
    IEEE DESIGN & TEST OF COMPUTERS, 1997, 14 (04): : 26 - 35
  • [9] Core design and system-on-a-chip integration
    Rincon, Ann Marie
    Cherichetti, Cory
    Monzel, James A.
    Stauffer, David R.
    Trick, Michael T.
    IEEE Design and Test of Computers, 1997, 14 (04): : 26 - 35
  • [10] Design and Implementation of an IP-core Based Safety-related Communication Architecture on FPGA
    Boercsoek, Josef
    Hayek, Ali
    Machmur, Bashier
    Umar, Muhammad
    2009 XXII INTERNATIONAL SYMPOSIUM ON INFORMATION, COMMUNICATION AND AUTOMATION TECHNOLOGIES, 2009, : 63 - 68