REDUCTION OF PN JUNCTION LEAKAGE CURRENT BY USING POLY-SI INTERLAYERED SOI WAFERS

被引：7
|
作者：
HORIUCHI, M
OHOYU, K
机构：
[1] Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 1995年 / 42卷 / 05期
关键词：
D O I：
10.1109/16.381983
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new type of silicon-on-insulator (SOI) structure was fabricated by using direct bonding technology to bury multilayered films consisting of poly-Si, Si3N4, and SiO2. The cross-sectional structures were analyzed by using SIMS, micro-Raman spectroscopy, and spreading resistance methods. Both the area components and the perimeter components of the pn-junction leakage current were reduced more than 10 fold in structures that had a poly-Si interlayer just beneath the active-devices to act as a gettering site. The leakage current was a function of tensile strength in the SOI layer and was easily controlled with a suitable combination of interlayered insulators.
引用
收藏
页码：876 / 882
页数：7
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