BIT-SERIAL MULTIPLIERS AND SQUARERS

被引：23

作者：

IENNE, P

VIREDAZ, MA

机构：

[1] Swiss Federal Institute of Technology, Mantra Centre for Neuro-Mimetic Systems

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1994年 / 43卷 / 12期

关键词：

D O I：

10.1109/12.338107

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Traditional bit serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus goad candidates for introduction in VLSI libraries.

引用

页码：1445 / 1450

页数：6

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