Spatially Distributed Dual-Spacer Null Convention Logic Design

Null convention logic allows designing power, area and speed-efficient asynchronous circuits while maintaining a standard cell-based design flow. This paper proposes a new logic template for null convention logic design. The template relies on the spatial distribution of different spacer values, using both return-to-one and return-to-zero handshake protocols. In order to compare this template with others, transistor level simulation of a Kogge-Stone adder serves as case study. Simulation results demonstrate that the proposed template allows better energy, static power and speed tradeoffs while furthering a standard cell-based approach.