Spatially Distributed Dual-Spacer Null Convention Logic Design

被引：10

作者：

Moreira, Matheus Trevisan ^{[1
]}

Trojan, Guilherme ^{[1
]}

Moraes, Fernando Gehm ^{[1
]}

Vilar Calazans, Ney Laert ^{[1
]}

机构：

[1] Pontificia Univ Catolica Rio Grande do Sul, Dept Informat, BR-90619900 Porto Alegre, RS, Brazil

来源：

JOURNAL OF LOW POWER ELECTRONICS | 2014年 / 10卷 / 03期

关键词：

Asynchronous Circuits; Quasi-Delay-Insensitive; Null Convention Logic; Four-Phase Protocol; Return-To-One; Return-To-Zero;

D O I：

10.1166/jolpe.2014.1332

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Null convention logic allows designing power, area and speed-efficient asynchronous circuits while maintaining a standard cell-based design flow. This paper proposes a new logic template for null convention logic design. The template relies on the spatial distribution of different spacer values, using both return-to-one and return-to-zero handshake protocols. In order to compare this template with others, transistor level simulation of a Kogge-Stone adder serves as case study. Simulation results demonstrate that the proposed template allows better energy, static power and speed tradeoffs while furthering a standard cell-based approach.

引用

页码：313 / 320

页数：8

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