共 50 条
- [42] Modeling and Characterization of Polymer-embedded Through-Silicon Vias (TSVs) in 3-D Integrated Circuits 2017 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS), 2017,
- [43] Development and Prospect of Coaxial Through-Silicon Via in 3D Integrated Circuits 2023 24TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY, ICEPT, 2023,
- [44] Study of the protrusion of through-silicon vias in dual annealing-CMP processes for 3D integration MICROSYSTEMS & NANOENGINEERING, 2025, 11 (01):
- [45] 3D Wafer Level Packaging: Processes and Materials for Through-Silicon Vias and Thin Die Embedding MATERIALS AND TECHNOLOGIES FOR 3-D INTEGRATION, 2009, 1112 : 43 - 53
- [47] Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits 2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION, 2009, : 322 - +
- [48] Reliable Through Silicon Vias for 3D Silicon Applications PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2009, : 63 - +
- [49] Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects 2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2010, : 1769 - 1775
- [50] A Silicon Interposer With an Integrated SrTiO3 Thin Film Decoupling Capacitor and Through-Silicon Vias IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, 2010, 33 (03): : 582 - 587