AN APPROACH TO THE ANALYSIS AND DETECTION OF CROSSTALK FAULTS IN DIGITAL VLSI CIRCUITS

被引：56
|
作者：
RUBIO, A
ITAZAKI, N
XU, XO
KINOSHITA, K
机构：
[1] BALER ISL UNIV,DEPT PHYS,PALMA DE MALLORCA,SPAIN
[2] UNIV POLITECN CATALUNA,DEPT ELECTR ENGN,ETSIT,CAMPUS NORD VPC,E-08034 BARCELONA,SPAIN
[3] OSAKA UNIV,FAC ENGN,DEPT APPL PHYS,SUITA,OSAKA 565,JAPAN
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1994年 / 13卷 / 03期
关键词：
D O I：
10.1109/43.265680
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The continuous reduction of the device size in integrated circuits and the increase in the switching rate cause parasitic capacitances between conducting layers to become dominant and cause logic errors in the circuits. Therefore, capacitive couplings can be considered as potential logic faults. Classical fault models do not cover this class of faults. In this paper we present a logic level characterization and fault model for crosstalk faults. We also show how a fault list of such faults can be generated from the layout data, and give an automatic test pattern generation procedure for them.
引用
收藏
页码：387 / 395
页数：9
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